In the '442 patent, the solder mounds are deposited respectively on a composite of contact metallization which comprises layers of chromium, copper, and gold which are vacuum deposited to provide the desired electrical contact to aluminum land 26. It is recognized in the art that the chromium deposit is necessary to establish the necessary isolation of the contact area such as clearly is illustrated in FIG. 3 of the '442 patent.
Reference is made to IBM Technical Disclosure Bulletin, Volume 16, No. 11, pp. 3610-3611 (Apr. 1974). This TDB discloses techniques of joining semiconductor chips to a substrate by means of a lead-indium solder joint. It is recognized, where controlled collapse chip connections (C4) are employed, isolation of the terminal area is required. Consequently, glass is used in one embodiment, chromium in another, ceramic in a third and silicon dioxide in a fourth implementation of the isolation structure.
In another known process, chromium-copper-chromium blankets are successively deposited onto the substrate. The deposition may be vacuum deposition or sputtering. The first layer of the chromium acts as an adhesion barrier between the copper layer and the ceramic or polyimide forming the substrate material. The intermediate copper layer is the conducting circuit layer as in the case of the '442 patent. The top chromium layer is employed as the solder stop-off or solder dam layer. Thus, as in the case of the '442 patent. this solder dam prevents run off of solder from the solder ball forming the C4 interconnection from contaminating adjacent portions of the substrate. Typically, the solder during collapse tends to run down the circuit line of the chip to be interconnected, thereby ruining that chip. Consequently, as recognized in the art, the top chromium layer is the key to having control collapse of the solder ball in achieving positive chip connection without run-off.
In accordance with this technique and by the extension of that described in the '442 patent, circuitization of the blanket layers, that is chromium-copper-chromium requires two complete photolithographic and etching processes. The first step defines the circuitry, or personalization and the second creates the solder dam. The second step is, therefore, a select etch. The photoresist of choice is currently KTFR. a negative photoresist. Etchant of choice is KMnO.sub.4 /KOH as a chromium etchant and FeCl.sub.3 /HCl as the copper etchant.
One of the difficulties in using this choice of materials is the inability of achieving fine line resolution. Another problem is that of stripping. Consequently, within the technology, there exists a limitation on line resolution which may be achieved and, therefore, overall density of the device. The potential use of a positive photoresist would provide a solution. However, a positive photoresist cannot be used because it is incompatible with the use of the top chromium layer. The incompatibility is that when the chrome layer is etched the positive photoresist will also be etched in the same step. Thus, given the use of chromium, the only reliable etchant used to date has been KMnO.sub.4 /KOH.
Another problem with the use of a negative photoresist such as KTFR is the use of the particular stripping material. J100 is currently employed. This material is considered aggressive and presents environmental and health problems Moreover, it must be used under extremely controlled conditions to prevent yield losses on the product.
Consequently, given the limitations in the technology, the definition of a system which would allow the use of a positive photoresist offers numerous advantages. However, to use standard positive photoresists, the requirement of top level chromium as a solder dam must be eliminated. This is because chromiumis etched by basic solutions such as NaOH or KOH which, in use would be destructive to the positive photoresist. Consequently, there existed prior to this invention no technique by which a positive photoresist can be used compatibly with a chromium solder dam layer.